The present invention relates to a decoder circuit, a decoding method, an output circuit, an electro-optical device, an electronic instrument, and the like.
An electronic instrument (e.g., electro-optical device) or a circuit (e.g., scan driver (gate driver)) included in an electronic instrument may include a decoder circuit (see JP-A-2007-043035 (FIG. 8C) and JP-A-2005-070673 (FIGS. 1 and 8), for example).
In FIG. 8C of JP-A-2007-043035, a level shifter section 76 of a scan driver 70 has level shifters in a number equal to the number of scan lines. An address decoder 74 of the scan driver 70 disclosed in JP-A-2007-043035 may be divided into two sections (e.g., decoders DCR-A and DCR-B disclosed in FIG. 1 of JP-A-2005-070673) in order to reduce the number of level shifters. However, since an incorrect scan voltage (glitch or noise) occurs in a scan line when a scan address signal generated by a scan address generation circuit 73 changes (i.e., when another scan line is selected), the scan driver 70 disclosed in JP-A-2007-043035 must be provided with a latch circuit such as a latch circuit LT shown in FIG. 1 of JP-A-2005-070673.